Integrated circuit die stacking techniques have been developed in which two or more integrated circuit devices are stacked vertically and interconnections are made between them using through-die vias. In conventional stacked-die fabrication processes that use through-die vias, conventional semiconductor fabrication process steps are performed on a semiconductor wafer so as to form a number of dice on the semiconductor wafer that are typically referred to as “base dice.” Each base die will include a number of through-die vias that that extend partially through the wafer substrate. The wafer is then flipped so that it is face-side down and it is attached to a wafer support structure. Grinding and polishing processes are then performed to remove material from the backside of the wafer and expose the through-die vias. The exposed through-die vias are then attached to another die, typically referred to as the “stacked die” or “daughter die” to complete the stacked-die structure.
Several attachment mechanisms are known in the art for attaching the semiconductor wafer to the wafer support structure. One of the best wafer-attachment mechanisms is thermally-released double-sided tape. More particularly, strips of double-sided tape are placed between the semiconductor wafer and the support structure, forming a structure that will keep the semiconductor wafer flat and supported during subsequent operations. One of the biggest advantages to the use of thermally-released double-sided tape is the fact that it is easy to separate the semiconductor wafer from the wafer support structure after the manufacturing process is complete, without damaging the semiconductor wafer. Though thermally-released double-sided tape is effective for attaching semiconductor wafers to wafer support structures, they have a low thermal budget (90-200° C.) that prevents subsequent high-temperature operations. More particularly, at temperatures that exceed the thermal budget, these tapes release, which can cause defects in the event of separation of the semiconductor wafer from the wafer support structure during a process step. Though a partial separation may sometimes only produce a decreased yield, often the semiconductor wafer curls, up requiring that the entire semiconductor wafer be scrapped.
Liquid adhesive materials such as epoxy can also be used. Typically, liquid adhesives are applied in liquid form and harden to fasten the semiconductor wafer to the wafer support structure. Though some of these liquid adhesive materials are quite effective for attaching the semiconductor wafers to wafer support structures, they also have low thermal budgets (typically having a maximum temperature of 150-250° C.).
One problem with the use of thermally-released double-sided tape and liquid adhesives having a low thermal budget is the fact that passivation of the backside of the wafer is not possible using conventional passivation processes. More particularly, conventional passivation processes require temperatures in excess of 300° C., making such processes unsuitable for stacked-die fabrication processes that use thermally-released double-sided tape and other low thermal budget materials.
Another problem with conventional fabrication processes for forming stacked-die assemblies using through-die vias are the potential defects that can result from the wafer-thinning process. More particularly, conventional wafer thinning processes use polishing process steps that directly polish the through-die vias. When the through-die vias are made of soft conductive material such as, copper, the over-polishing processes can result in smearing of the metal. This can lead to undesired capacitance, current leakage, and in severe cases could lead to short circuits on the backside of the wafer. Moreover, conventional polishing and grinding processes often create nonuniformities near through-die vias (e.g., local regions that are not planar with the rest of the surface being ground or polished). The occurrence of localized nonuniformities near through-die vias is particularly apparent when the base die has only a small number of through-die vias.
Accordingly, there is a need for a method for forming a stacked-die assembly having a passivation layer on the backside of the semiconductor wafer. Also, there is a need for a process for forming a stacked-die assembly having a passivation layer that will not violate the thermal budget of the thermally-released double-sided tape or the liquid adhesive used to attach the semiconductor wafer to the wafer support structure. In addition, there is a need for a process for forming a stacked-die assembly that does not have through-die via metal smearing and that does not have localized nonuniformities near through-die vias resulting from the wafer thinning process.